This application is based on Japanese Patent Application HEI 11-146707, filed on May 26, 1999, the entire contents of which are incorporated herein by reference.
a) Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices whose impurities are activated through laser annealing and to such semiconductor devices.
b) Description of the Related Art
A conventional general manufacture method for MOS transistors will be described first. After element separation regions are formed in the surface layer of a silicon substrate to define active regions, impurities are doped in the active regions for the control of threshold voltage. A gate electrode is formed on each active region, and impurities are doped shallowly into source/drain regions on both sides of the gate electrode. Side wall spacers are formed on the side walls of the gate electrode, and impurities are doped deeply into source/drain regions outside the side wall spacers. Rapid thermal annealing (RTA) is performed to activate the impurities doped into the source/drain regions.
As MOS transistors are formed finely and the channel resistance lowers, the resistance of the source/drain regions increases relatively. The resistance of the source/drain regions of a MOS transistor having a gate length of 0.1 xcexcm becomes as large as 30 to 50% of the total resistance. The main factor of raising the resistance of the source/drain regions is the shallow junction portion under the side wall spacer. If the activated impurity concentration in this shallow junction portion is raised to lower the resistance thereof, parasitic resistance of the source/drain regions can be lowered.
It is difficult to activate impurities having a concentration of 1xc3x971020 cmxe2x88x923 by using RTA. Impurities having a higher concentration can be activated if laser annealing techniques are utilized. If the concentration of impurities in the shallow junction portion under the side wall spacer is raised by laser annealing, the resistance of the shallow junction portion can be lowered.
Although the parasitic resistance of the source/drain regions can be lowered by laser annealing, it has been found that MOS transistors manufactured by using laser annealing techniques have a low threshold voltage and an increased off-current.
It is an object of the present invention to provide a method of manufacturing a semiconductor device, capable of lowering a parasitic resistance of source/drain regions and making its threshold voltage hard to be lowered.
It is another object of the present invention to provide a semiconductor device having a low parasitic resistance of source/drain regions and a desired threshold voltage.
It is another object of the present invention to provide a method of manufacturing a semiconductor device capable of lowering a contact resistance between an impurity diffused region and a connection wire.
According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a step of forming a gate electrode in a partial area of a surface of a semiconductor substrate; a first impurity implantation step of implanting impurities of a first conductive type into the semiconductor substrate in areas on both sides of the gate electrode, by using the gate electrode as a mask; a step of activating the impurities implanted by the first impurity implantation step by applying a laser beam to the surface of the semiconductor substrate; a step of implanting impurities for controlling threshold voltage into a surface layer of the semiconductor substrate under the gate electrode, after the laser beam is applied; and a step of activating the impurities for controlling threshold voltage by heating the semiconductor substrate.
Activation of impurities by laser annealing can increase the concentration of activated impurities more than activation by RTA. Parasitic resistance of a semiconductor device can therefore be lowered.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: implanting first impurities of a second conductive type into a surface layer of a semiconductor substrate in an area doped with impurities of a first conductive type opposite to the second conductive type; forming an impurity diffusion region of the second conductive type having a p-n junction at a first depth from a surface of the semiconductor substrate, by heating the semiconductor substrate and activating the first impurities; implanting second impurities of the second conductive type in a shallower area than the first depth in the impurity diffusion region; and activating the second impurities by applying a laser beam to the surface of the semiconductor substrate.
The impurity diffusion region formed by laser radiation is in the impurity diffusion region of the same conductive type as the first-mentioned impurity diffusion region. Although defects are generated near the boundary between the impurity diffusion region activated by laser radiation and the region around the impurity diffusion region, they are not generated near the p-n junction interface. It is possible to prevent an increased leak current to be caused by defects.
As above, the shallow junction portion in the source/drain region in contact with the channel is formed by laser annealing so that the concentration of activated impurities can be made high. Parasitic resistance of the source/drain regions can be lowered. Since impurities for controlling threshold voltage are implanted into the channel region after laser annealing, it is possible to set impurity concentration in the channel region for desired value. It is therefore possible to prevent the threshold voltage from being lowered and the off-current from being increased.